1. Field of the Invention
The present invention relates generally to source synchronous communication links and, more particularly, to debugging data capture problems on source synchronous communication links.
2. Related Art
Chipsets and other devices communicate over a trace, bus, wire or other communication link or channel. External clocks are often used to synchronize the timing between such communicating components. Typically, with regard to chipsets, an external clock chip generates a system clock that is routed throughout the circuit board to different components for translation into an internal clock. The internal clock is then used by the individual components to generate internal and external signals. The extended routing of the system clock combined with the translation of the system clock to an internal clock by individual components results in timing variations at the interface of the different components. For systems operating at a low frequency most such-timing variations can be absorbed by a longer system clock cycle while more extreme timing variations can be bypassed through the addition of wait states to the valid time of a signal.
Recent advances in microprocessor technology have provided processors with substantially greater operating frequencies. To fully utilize the benefits provided by such microprocessors, system clock speeds must be increased. As the system clock speeds have increased, common-clocked, data transfer systems developed problems such as flight time delays, clock skews, etc.
To overcome these communication problems source synchronous communication techniques have been developed. In a source synchronous environment, clock or strobe signals are sent between components along with the data signals to communicate timing information. Instead of having one or more components operate on a common clock signal, data is communicated at a speed that is not set by a common clock signal. The strobe signal sent with the data may be used, for example, to start an internal clock, for latching of the data, or for other timing purposes. In this way, source synchronous communication eliminates many of the noted problems of traditional, common-clocked, data transfers, thereby providing increased data transfer rates over traditional data transfer schemes.
The term “data eye” is commonly used to describe the shape of the data waveform as it has a shape resembling a partially closed eye. Typically, the data strobe, which may be a single or two differential signals, is skewed so that it is phase shifted by 90 degrees (centered) with respect to the data signal with which it is sent. That is, a rising or falling edge of the data strobe falls close to the center of the data eye. This guarantees that each data bit is stable at the source synchronous receiver at the time of receipt of the corresponding clock signal, increasing the likelihood that the data will be properly latched into the source synchronous receiver.
Unfortunately, however, a high-speed source synchronous communication link is susceptible to electrical data capture errors. Electrical characteristics of the link such as connector quality, length of trace lines, capacitive and inductive coupling, cross-talk and the like degrade the integrity of the data signal; that is, diminish the size of the data eye. The timing and noise margins of the data signals, which are determined by the width and height, respectively, of the data eye, are likewise decreased. For high-speed communication links, these reductions, particularly in the timing margin, prevent the communication link from operating at the targeted frequencies.
A number of traditional approaches have been suggested to determine whether data capture errors have occurred. One conventional approach has been to use scan-on-the-fly (SOTF) techniques. Such techniques, which are commonly used to capture data located in internal registers in the core of a chip, require the addition of a debug flip-flop coupled to the output of each of the data capture flip-flops. Such shadow flip-flops receive the captured data as it is output from the data capture flip-flop. The captured data can then be made available for subsequent analysis. One drawback to this approach is that since a debug flip-flop must be coupled to each data capture flip-flop, twice as many flip-flops must be implemented, drastically increasing the requisite area consumed by the receiving device. More importantly, perhaps, is the increased capacitive loading that is placed on the data capture flip-flops, which may be significant depending on the distance between the shadow flip-flop and its corresponding data capture flip-flop. This increased capacitive loading on the data capture flip-flops increases the latency of the data path, further reducing the timing margins.
Another approach has been to scan the captured data directly from the data capture flip-flops. However, to scan the data from the flip-flops, additional devices such as a multiplexer must be implemented in the functional data path to control the clock provided to the data capture flip-flops. Such additional components in the functional data path increase the latency of the data path, further reducing the timing margins.
What is needed, therefore, is an apparatus and methodology for optimizing the timing margins of a source synchronous communication link and for determining the data capture capability of a source synchronous link without introducing additional logic, area or latency in the functional data path.